Due to high quality, compactness, and low power display, a flat panel display device such as a TFT (thin film transistor) type liquid crystal display device is widely used as a display device in personal computers (such as laptops), mobile telephones, and the like.
A flat panel display device includes a plurality of data lines and a plurality of scan lines. Active elements, such as TFTs, are arranged in a matrix at intersections of data lines and scan lines. When a selection voltage is supplied to a corresponding scan line, corresponding active elements (in the row formed by the corresponding scan line) are turned on and voltages supplied to the data lines are accumulated in display cells (for example, on a liquid crystal element). When the scan line is in a non-selection state, the voltages accumulated in the display cells are held to be imparted to a liquid crystal, thereby conducting display. A display cell is provided corresponding to each dot (pixel) of image display data and controlled such that the voltage level stored is changed according to a gray level of each dot display. In addition, when color display is conducted, three display cells each having one of three primary colors are provided for each dot and respective gray levels of the three primary colors are controlled by the voltages held in each of the three display cells to conduct color display.
A display control circuit includes a source driver for driving the source line which can be a data line. Referring now to FIG. 10, a circuit schematic diagram of a conventional source driver is set forth and given the general reference character 1000. Conventional source driver 1000 is disclosed in Japanese Patent Application Laid-Open 4-242788 A (JP 4-242788 A). In conventional source driver 1000, image data of each pixel is provided on a data bus DIN as digital data. Bus DIN is connected with a plurality of output cells (1003-1 to 1003-N). Gray level voltages (VR1 to VR64) are provided to respective output cells (1003-1 to 1003-N) from a γ power source generating circuit 1. According to the description, in a display device for conducting a 64-gray level display for respective colors of red (R), green (G), and blue (B), 64 gray level voltages (VR1 to VR64) are generated. These voltages are obtained from respective contact points between 65 resistors connected in series between power sources (4-1 and 4-2). Resistance values of the respective resistors connected in series are not uniform but are resistance values γ-corrected such that light and dark in the respective gray levels are natural gray levels when viewed by a person.
The image data to respective source lines of the display device are serially transferred to the data bus DIN. Each output cell (1003-1 to 1003-N) includes a latch 31, a digital to analog (D/A) converter 32 and a class AB amplifying circuit 1034. When corresponding image data is transferred in response to a data latch signal DL, latch 31 latches the data. The output of latch 31 is provided to a D/A converter 32. D/A converter decodes the image data to select and provide a corresponding gray level voltage (VR1 to VR64). The output of D/A converter 32 is provided to the non-inverting input of class AB amplifying circuit 1034. Class AB amplifying circuit 1034 is an operational amplifier in which the output is directly fed back to the inverting input. Class AB amplifying circuit 1034 operates as a voltage follower. Class AB amplifying circuit 1034 provides a buffer function for the gray level voltage (VR1 to VR64) provided at an output terminal (PS-1 to PS-N) for a corresponding output cell (1003-1 to 1003-N).
Each output terminal (PS-1 to PS-N) is connected to a corresponding source line of the display device. Thus, each output terminal (PS-1 to PS-N) has an extremely large load capacitance. Accordingly, each output terminal (PS-1 to PS-N) is driven by a class AB amplifying circuit 1034 providing a buffer, so that high-speed operation may be achieved.
However, because each source line has an extremely large load capacitance, an extremely high current drive capacity can be desirable for the class AB amplifying circuit 1034. As a result, even after an output terminal (PS-1 to PS-N) is driven up to a target gray level voltage (VR1 to VR64), class AB amplifying circuit 1034 consumes current through a driver circuit portion that provides a current path from a high voltage level to a low voltage level through the output terminal (PS-1 to PS-N). In addition, the current increases proportionally to an increase in size of the transistors in the driver circuit portion of class AB amplifying circuit 1034. Thus, even if a gray level voltage (VR1 to VR64) provided to an output terminal (PS-1 to PS-N) is not changed, class AB amplifying circuit 1034 can consumes an extremely large amount of power.
Referring now to FIG. 11, a circuit schematic diagram of a conventional source driver is set forth and given the general reference character 1100. Conventional source driver 1100 is disclosed in Japanese Patent Application Laid-Open 10-326084 A (JP 10-326084 A). Conventional source driver 1100 differs from conventional source driver 1000 in that class AB amplifying circuit 1034 is not included in output cells (1103-1 to 1103-N). Instead a buffer circuit 1102 is included between γ power source generating circuit 1 and output cells (1103-1 to 1103-N) to provide gray level voltages (VR1 to VR64). Otherwise, conventional source driver 1100 has the same configuration as conventional source driver 1000 and therefore the same reference characters are provided therefore.
Buffer circuit 1102 drives an output terminal (PS-1 to PS-N) together with an internal bus line for supplying the gray level voltage (VR1 to VR64). As a result, in conventional source driver 1100, it is necessary to further increase the current capacity of the transistors in the output portion of each class AB amplifying circuit in buffer 1102 as compared to class AB amplifying circuit 1034 in conventional source driver 1000. In this way, power consumption is further increased.
According to conventional source drivers (1000 and 1100), buffers including class AB amplifying circuits for high-speed operation can have large power consumption.
In recent years, the use of flat display devices has increased. When used in a portable device or the like, it is desirable for power consumption to be minimized to increase battery lifetime.
In order to further reduce power consumption while maintaining substantially high speed operation, a conventional source driver is disclosed in Japanese Patent Application laid-open no. 11-305744 A (JP 11-305744 A). Referring now to FIG. 12, a circuit schematic diagram of a conventional output cell of a conventional source driver is set forth and given the general reference character 1200. Conventional output cell 1200 is disclosed in JP 11-305744 A. In conventional output cell 1200 of a conventional source driver, image digital data DIN and gray voltage levels (V1 to VM) are provided to a decoder 1230. Decoder 1230 selects and provides a gray level voltage (V1 to VM) according to a value of data DIN. Thus, decoder 1230 is equivalent to a D/A converter (32 and 1133) illustrated in conventional source drivers (1000 and 1100), respectively. However, in conventional output cell 1200 of a conventional source driver, an output terminal OUT is driven by a voltage follower configured operational amplifier circuit 1234. Operational amplifier circuit 1234 serves as a buffer and can be made active or inactive in response to a control signal CONT. According to conventional output cell 1200, when control signal CONT has an active level (low level), operational amplifier circuit 1234 is activated and drives output terminal OUT. On the other hand, when control signal CONT has an inactive level (high level), the operational amplifier circuit 1234 is disabled or inactive and has a high impedance output. In this way, the power consumption of operational amplifier circuit 1234 becomes substantially zero.
Conventional output cell 1200 includes a switch circuit 1236 connected between the output of decoder 1230 and output terminal OUT. Switch circuit 1236 includes an inverter 1238 and a transmission gate TG1. When control signal CONT becomes a high level, switch circuit 1236 is turned on and transmission gate TG1 provides a low impedance path between the output of decoder 1230 and output terminal OUT. In this way, when control signal CONT is in the inactive level, operational amplifier circuit 1234 is disabled and the gray level voltage (V1 to VM) is provided to output terminal OUT directly by decoder 1230 through transmission gate TG1.
Therefore, every time new image data DIN is supplied, control signal CONT becomes a low level and output terminal OUT is driven to a gray level voltage (V1 to VM) or its vicinity by operation amplifier circuit 1234 at a high speed. After that, the control signal CONT transitions to a high level so that operational amplifier circuit 1234 is disabled so that power consumption is reduced and output terminal OUT is directly driven by decoder 1230 to a gray level voltage (V1 to VM). Thus, according to conventional output cell 1200, power consumption is reduced while keeping a substantial high-speed operation.
According to conventional output cell 1200 of a conventional source driver, control signal CONT is used to commonly control buffer operational amplifier circuit 1234 and switch circuit 1236, thus, the operation/non-operation timings of the respective elements are provided by control signal CONT. However, times required for charging and/or discharging a display cell and a source line vary greatly according to a display pattern. For example, charging the display cell and source line up to 4.8 V when each have an initial voltage of 0.2 V takes a long time. In contrast to this, when the display cell and the source line each initially have a potential of 4.8 V, providing a 4.8 V takes no time or current. However, switching control signal CONT in consideration of the times required for charging and/or discharging the source line according to the display pattern may be substantially impossible. If control signal CONT is switched to the inactive level too early, a desired gray level may not be obtained because the source line and display cell has not been sufficiently charged or discharged. On the other hand, if control signal CONT is switched to the inactive level too late, excess current is consumed by operational amplifier circuit 1234 and current consumptions benefits are reduced.
Furthermore, a design of a conventional source driver using conventional output cell 1200 may be complicated due to the generation of control signal CONT to provide such timing.
In view of the above discussion, it would be desirable to provide a display control circuit as a source driver in which high-speed operation may be conducted without conventional timing control as shown above. It would also be desirable to provide a display control circuit as a source driver in which high-speed operation may be conducted while lower power consumption may be realized.